FIG. 14 is a block diagram of a phase lock circuit(phase-locked loop circuit) PS111 according to the prior art.
The phase lock circuit PS111 comprises a phase comparator 1i, a loop filter 2i, a voltage control oscillator(voltage-controlled oscillator) 3i, a signal input terminal 7i and a signal output terminal 9i. The phase comparator 1i is formed by an EXOR circuit.
FIG. 15 (1) shows the waveform of an input signal 7i (VIN); FIG. 15 (2) shows the waveform of the output from the voltage control oscillator 3i; FIG. 15 (3) shows the waveform of the output from the phase comparator 1i; and FIG. 15 (4) shows the waveform of the output from the loop filter 2i. 
It is assumed therein that the duty ratio of the pulse of the input signal 7i (VIN) shown in FIG. 15 (1) and the pulse of the voltage control oscillator 3i shown in FIG. 15 (2) is equal to 50%.
As shown in FIG. 15 (3), the duty ratio in the phase comparator 1i is determined by the leading edge timing in the pulse of the input signal 7i (VIN) shown in FIG. 15 (1) and the leading edge timing in the output pulse of the voltage control oscillator 3i shown in FIG. 15 (2).
The output level of the loop filter 2i shown in FIG. 15 (4) is determined by the duty ratio of the phase comparator 1i shown in FIG. 15 (3) while the oscillation frequency of the voltage control oscillator 3i is determined by the output level of the loop filter 2i. 
Namely, in the phase lock circuit PS111 of the prior art shown in FIG. 14, the phase difference between the pulse of the input signal 7i (VIN) shown in FIG. 15 (1) and the output pulse of the voltage control oscillator 3i shown in FIG. 15 (2) determine the oscillation frequency of the voltage control oscillator 3i. 
When the phase lock circuit PS111 is in its locked state, the above-mentioned phase difference is determined such that the frequency (or bit rate) of the input signal 7i (VIN) shown in FIG. 15 (1) coincides with the output frequency of the voltage control oscillator 3i. 
FIG. 15 (1) shows a case where the phase difference is equal to 125 while FIG. 15 (2) shows another case where the phase difference is equal to 90.
If the control coefficient of the voltage control oscillator 3i (or ratio between the control voltage and the output frequency) is positive and when the right-side graphs (II) of FIG. 15 are reference, the left-side graphs (I) of FIG. 15 illustrate that the frequency (or bit rate) of the input signal 7i (VIN) is higher.
FIG. 16 shows changes in the output voltage of the loop filter 2i when the frequency (or bit rate) of the input signal 7i (VIN) is changed.
The phase lock circuit PS111 is in its locked state in the middle area of the lock range (or area between the lower and upper ends of the lock range).
As the frequency (or bit rate) of the input signal 7i (VIN) varies, the aforementioned phase difference also varies to change the duty ratio in the output signal of the phase comparator 1i and the output voltage of the loop filter 2i. 
However, the duty ratio has the lower limit (0%) and the upper limit (100%). In other words, the limits of the duty ratio in the output of the phase comparator 1i exist in the upper and lower ends of the lock range.
If the phase lock circuit is to be applied to the communication system, the parameters of the phase lock circuit (e.g., loop filter bandwidth and gain) must be determined such that the specification of a frequency synthesizer such as phase noise characteristic or the specification of CDR such as jitter tolerance will be satisfied. This raises a problem in that a sufficiently broad lock range cannot be provided.
If the lock range is not sufficiently broad and when a drift occurs in the oscillation frequency due to various environmental variations such as the aged deterioration of the voltage control oscillator (VCO), temperature change and supply voltage variation, there is raised a problem in that the lock cannot be held. In addition, the oscillation frequency of the voltage control oscillator must accurately be pre-regulated on shipment.
If the phase lock circuit additionally includes a retraction circuit (see Japanese Patent Application No. Hei 8-130468), it raises still another problem in that the lock range would extremely be reduced.
The retraction circuit is added to the phase lock circuit for enlarging the pull-in range therein. When the phase lock circuit is in its unlock state, the retraction circuit inputs a scanning signal into the voltage control oscillator to change the oscillation frequency greatly. As the oscillation frequency approaches to the frequency of the input signal, the retraction circuit retracts the phase lock circuit. Thereafter, the locked state of the phase lock circuit is detected and the phase lock circuit is controlled to hold the voltage in the scanning signal, thereby maintaining the locked state thereof.
However, the retraction circuit does not have a function of lock-range enlargement. If the retraction circuit retracts the oscillation frequency at the end of the lock range, the substantial lock range (or minimum distance between the retracting frequency and the lock range end) will extremely be reduced. This raises a further problem in that the locked state will not be maintained stable.
An object of the present invention is provide a phase lock circuit which can provide a very broad lock range even if the lock range is reduced by regulating the parameters of the phase lock circuit to satisfy the jitter tolerance and so on or even if the lock range is substantially reduced by adding the retraction circuit into the phase lock circuit.
FIG. 17 is a block diagram of another phase lock circuit PS112 according to the prior art, into which a retraction circuit according to the prior art is added.
The phase lock circuit PS112 comprises a phase comparator 1n, a loop filter 2n, a voltage control oscillator 3n, a signal input terminal 7n, a signal output terminal 9n, a lock detector 21n, an additional loop or retraction circuit FS1 and an adder 6. The phase comparator in, loop filter 2n and voltage control oscillator 3n together define the main body of the phase lock circuit. The retraction circuit FS1 comprises a pulse generator 23n, a counting circuit 24n and a D/A converter 25n, as shown in Japanese Patent Application No. Hei 8-130468.
The retraction circuit FS1 is added to the phase lock circuit for enlarging the pull-in range therein. When the phase lock circuit is its unlocked state, the retraction circuit FS1 inputs a scanning signal to the voltage control oscillator 3n to change the oscillation frequency thereof greatly. As the oscillation frequency approaches to the frequency of the input signal, the retraction circuit FS1 retracts the phase lock circuit. Thereafter, the locked state of the phase lock circuit is detected. At this time, the retraction circuit controls the phase lock circuit to hold the voltage of the scanning signal and to maintain the locked state of the phase lock circuit.
FIG. 18 shows waveforms in the primary parts of the phase lock circuit PS112 into which the retraction circuit is added.
FIG. 18 (1) shows the waveform in the output signal of the loop filter 2n; FIG. 18 (2) shows the waveform in the output signal of the lock detector 21n; FIG. 18 (3) shows the waveform in the output signal of the pulse generator 23n; and FIG. 18 (4) shows the waveform in the output signal of the D/A converter 25n. 
In the initial stage of the time chart (left side about a dotted line), the phase lock circuit PS211 is in its unlocked state which is discriminated by the lock detector 21n. The pulse generator 23n produces a pulse. In association with this, the counting circuit 24n varies its count while the D/A converter 3n changes its output voltage in a stepwise manner. The output, voltage of the D/A converter 25n varies the oscillation frequency of the voltage control oscillator 3n. As the oscillation frequency approaches to the frequency of the input signal, the phase lock circuit is retracted. Thereafter, the lock detector 21n discriminates the locked state of the phase lock circuit and the pulse generator 23n is stopped. The counting circuit 24n maintains its count constant while the D/A converter 25n maintains its output voltage constant to hold the locked state of the phase lock circuit. As a result, the pull-in range can be enlarged within a range in which the oscillation frequency of the voltage control oscillator 3n is variable.
On the other hand, there exists the output voltage range of the D/A converter 25n in which the locked state of the phase lock circuit can be maintained (see FIG. 18 (4)). However, the actuation of the lead-in(retraction) circuit not necessarily causes the output signal of the D/A converter 25n to occur at a position near the center of this voltage range. If the locked state is maintained at a position near the lower (or upper) limit of the lock range as shown in FIG. 18 (4), the substantial lock range (or minimum distance between the retracting frequency and the lock range end) will extremely be reduced. In such a case, the locked state cannot be maintained stable due to the subsequent environmental variation such as supply voltage variation, temperature change, jitter input).
Even if the phase lock circuit is unlocked, it will again be retracted by the lead-in(retraction) circuit. However, this raises further problems in that a spurious radiation occurs during a period between the unlocking and the completion of re-retraction (if the phase lock circuit is applied to a frequency synthesizer) and in that the data is lost (if the phase lock circuit is applied to CDR).
The present invention is to provide a phase lock circuit which can enlarge the lock range thereof and maintain the locked state stable, even though the above-mentioned lead-in(retraction) circuit is added to the phase lock circuit.